New - Aspeed Ast2500 Datasheet
Does the new datasheet hint at an AST2500+? Indirectly, yes. ASPEED has confirmed via the new datasheet's "Ordering Information" section that the (active) and AST2500L-A2 (industrial temp) are the final silicon steppings. No A3 is expected.
The AST2500 includes an ECC-enabled SPI flash controller. However, the original documentation was ambiguous. The new revision provides explicit code examples for initializing ECC regions for the boot loader. Failure to follow the "new" sequence results in a 30% chance of boot failure after power cycling due to "Flash Uncorrectable Error" flags. aspeed ast2500 datasheet new
The original datasheet claimed H.264 encoding. The new datasheet reveals support for multi-stream compression . You can now encode one stream for KVM (low bandwidth) and another for local recording simultaneously. The register set for VE_OFFSET_CTRL has been expanded to handle two logical channels. Does the new datasheet hint at an AST2500+
"SPI flash corruption during Write Protect toggle." Solution (New Sheet): The new timing diagram shows that the WP# pin has a 10ns minimum hold time after CS# rises. Most legacy drivers set 0ns; this causes corruption in high-temperature environments. No A3 is expected
A major headache in older designs was bus contention on I2C channels 0 and 1. The new datasheet introduces a "bus park" mode register (0xE000_01C4) that prevents the BMC from locking the bus during host reset cycles.
